Processor speeds are outpacing primary memory performance, with both processor designers and system manufacturers developing higher performance memory subsystems in an effort to minimize memory performance limitations. Ideally, the memory performance would match or exceed processor performance, i.e., a memory cycle time is less than one processor clock cycle. However, this often is not the case and, thus, the memory may be a system bottleneck.
There are two common families of RAM memory devices used as primary storage directly accessible by the microprocessor. A static random access memory device (SRAM) is based on flip-flop circuits and retains data as long as power is supplied. A dynamic random access memory device (DRAM) stores data as a function of a charge on a capacitor. The capacitor must constantly be refreshed since the charge dissipates. DRAMs are relatively inexpensive to fabricate but are slow as compared to SRAMS. SRAMs are therefore typically, reserved for use as caches. In both cases, data is clocked out of the RAM on either the rising or falling edge of a clock pulse.
Innovations in RAM technology have lead to a device referred to as the Double Data Rate (DDR) RAM. The DDR RAM allows reads and writes at twice the frequency of the applied clock (e.g., at frequencies greater than 400 to 600 MHz) by moving data on both rising and falling clock edges. However, to recognize the double-data-rate signal in the DDR architecture, the cache control logic of the processor may need to be modified. With normal cache SRAM, for each processor clock cycle the SRAM delivers one piece of data, whereas with DDR there is one piece of data on the rising edge and another piece of data on the falling edge of the clock. Furthermore, the high-end network application specific integrated circuit (ASIC) typically has a wide SRAM data interface which includes multiple high-speed DDR SRAM chips. Therefore, if one SRAM is faster than another SRAM, the data from the two SRAM chips may be skewed substantially enough to make synchronous data sampling difficult to achieve in such fast data interface environment.